说明
Working Condition Warranty Available配置
J750EX 1024 Test Head, Tera1, Teradyne Manipulator, 1x CUB, 8x HSD200, 4x DPS, 1x CTO, 4x DSMTO Reconfiguration is supportedOEM 型号描述
The J750Ex is a low cost, high efficiency parallel test system for advanced microcontrollers and consumer SoC package test & wafer sort. It is built on the foundation of the J750, one of the most successful test platforms in ATE history. The J750Ex provides highly economical parallel test solutions for high-performance microcontrollers, consumer SoC devices, and digital wafer sort applications. It offers high parallel test configuration with 50% higher throughput and 99% parallel test efficiency. All J750 systems are DIB compatible and can run tens of thousands of J750 test programs. The J750Ex has a range of features including up to 1024 digital pins, 96 device power supplies, and analog test capability, as well as enhanced DFT capability with 196 Gbit scan depth and deep diagnostic capture. It also has a per-pin test architecture, pattern-controlled instrumentation, and flexible site mapping with no slot boundaries. The system is air-cooled and has a “Zero footprint” tester-in-a-test-head design for minimum floor space.文件
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TERADYNE
J750EX
已验证
类别
Final Test
上次验证： 60 多天前
物品主要详细信息
状况：
Used
运行状况:
未知
产品编号：
82940
晶圆尺寸：
未知
年份：
未知
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
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TERADYNE
J750EX
类别
Final Test
上次验证： 60 多天前
物品主要详细信息
状况：
Used
运行状况:
未知
产品编号：
82940
晶圆尺寸：
未知
年份：
未知
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
说明
Working Condition Warranty Available配置
J750EX 1024 Test Head, Tera1, Teradyne Manipulator, 1x CUB, 8x HSD200, 4x DPS, 1x CTO, 4x DSMTO Reconfiguration is supportedOEM 型号描述
The J750Ex is a low cost, high efficiency parallel test system for advanced microcontrollers and consumer SoC package test & wafer sort. It is built on the foundation of the J750, one of the most successful test platforms in ATE history. The J750Ex provides highly economical parallel test solutions for high-performance microcontrollers, consumer SoC devices, and digital wafer sort applications. It offers high parallel test configuration with 50% higher throughput and 99% parallel test efficiency. All J750 systems are DIB compatible and can run tens of thousands of J750 test programs. The J750Ex has a range of features including up to 1024 digital pins, 96 device power supplies, and analog test capability, as well as enhanced DFT capability with 196 Gbit scan depth and deep diagnostic capture. It also has a per-pin test architecture, pattern-controlled instrumentation, and flexible site mapping with no slot boundaries. The system is air-cooled and has a “Zero footprint” tester-in-a-test-head design for minimum floor space.文件
无文件