说明
无说明配置
无配置OEM 型号描述
The Eclipse Mark IV is the latest generation PVD tool from the highly successful Eclipse family. It offers the lowest Cost-of-Ownership through high throughput, a small footprint, and high reliability with exceptional process performance. The system achieves high throughput in a high vacuum environment through the use of serial wafer handling, resulting in 80% fewer wafer transfers than a traditional cluster tool. The Eclipse Mark IV has a footprint of 44 square feet and can be configured for etch or deposition, providing full capability for today’s contact, barrier, interconnect, resistor, and packaging films for Silicon, GaAs and CCD substrates. Wafer temperature is regulated by backplane heaters and the chambers have world class vacuum leak rates and base pressures.文件
无文件
TEL / MRC
ECLIPSE MARK IV
已验证
类别
PVD / Sputtering
上次验证： 60 多天前
物品主要详细信息
状况：
Used
运行状况:
未知
产品编号：
79338
晶圆尺寸：
6"/150mm
年份：
未知
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
类似上架物品
查看全部
TEL / MRC
ECLIPSE MARK IV
类别
PVD / Sputtering
上次验证： 60 多天前
物品主要详细信息
状况：
Used
运行状况:
未知
产品编号：
79338
晶圆尺寸：
6"/150mm
年份：
未知
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
说明
无说明配置
无配置OEM 型号描述
The Eclipse Mark IV is the latest generation PVD tool from the highly successful Eclipse family. It offers the lowest Cost-of-Ownership through high throughput, a small footprint, and high reliability with exceptional process performance. The system achieves high throughput in a high vacuum environment through the use of serial wafer handling, resulting in 80% fewer wafer transfers than a traditional cluster tool. The Eclipse Mark IV has a footprint of 44 square feet and can be configured for etch or deposition, providing full capability for today’s contact, barrier, interconnect, resistor, and packaging films for Silicon, GaAs and CCD substrates. Wafer temperature is regulated by backplane heaters and the chambers have world class vacuum leak rates and base pressures.文件
无文件